1. Field of the Invention
This invention relates to high density microminiaturized electronic circuit devices. More particularly, this invention relates to multilevel structures, and the formation of multilevel structures, comprised of alternating via levels and wiring levels embedded in a low dielectric constant medium and mounted on chip carriers.
2. Background of the Invention
Electrically integrated structures having multiple levels of conductive wiring horizontally supported in or on a dielectric material and vertically separated by intermediate levels of dielectric material are well known. Typically, alternating levels of wiring and vias can be quite numerous and complex in layout. The continuing drive toward reduction in dimensions and increase in density of features within these structures is inspired by aggressive requirements of memory, logic and storage density. Smaller device structures result in higher bit density, lower operating voltage, lower energy consumption and faster device speed. Smaller device structures require proportionately narrower and shorter conductor lines, narrower diameter vias and lower dielectric constant materials.
Increased also are the problems associated with such miniaturization and the proximity of the features to one another, including the risks of shorting, crosstalk and capacitive coupling between and especially within wiring levels, additional heat generation due to IR drop and the risk of failure due to electromigration and impeded signal speed.
As the design of the multilevel circuit structures becomes more aggressive, the need to reduce the dielectric constant (Er) of the dielectric insulating material to a value closer to the ideal value of value 1.0 in air or vacuum becomes a necessity. The lower the Er, the faster the signal speed and the rise time and the less the capacitive interaction. Lower Er permits operation of the device at a lower voltage which will result in lower thermal heating due to IR drop. In highly compact IC structures, the Er must be lowered not only in the via interlevels between wiring levels, but more importantly intralevelxe2x80x94within each wiring level. It is more critical to obtain extremely densely patterned circuitry levels separated by extremely low Er dielectric material between adjacent conductor lines within each wiring level to avoid capacitative interaction within the dense wiring levels. The lower the Er, the closer to each other can the lines in a wiring level be placed. It is therefore in the wiring level that the dielectric medium is more beneficially air, another suitable gas, or vacuum, i.e. a hollow structure.
Heat conductors in via levels and horizontal air movement through a hollow structure assure the elimination of any xe2x80x9chot spotsxe2x80x9d. Hot spots would contribute greatly to stress induced electromigration. Likewise, removing the additional heat generated by the densely configured operating structure and maintaining a low weight contribution to the ultimate device, for example such as laptop and hand-held devices, are important problems to solve in building high performance structures of the future.
Various materials, such as polyimide, epoxies, FR4-type resins, cyclotene, polymethyl methacrylate (PMMA) and Novolac-type resins, as well as fluorocarbons and others have been used as dielectric material in multilevel packaging structures, often with additives and fillers to affect properties such as thermal expansion (to reduce cracking and dislocation resulting from differing coefficients of thermal expansion among materials used in the structure), flame retardance, and Er. A high performance dielectric material might have an Er of about 3.2 to about 5.0; a pure fluoropolymer might have an Er as low as 2.1, a polyimide about 3.1 to about 3.5. In order to reduce further the Er to a number more nearly approaching the ideal value of pure air, various materials such as foam or hollow microspheres have been added to the resinous dielectric, the latter as described in U.S. Pat. No. 5,126,192 issued Jun. 30, 1992 to Chellis et al. and assigned to the assignee of the present invention. As the dimensions of the circuitry and particularly the spaces between the individual conductor lines on any one level continue to decrease it is becoming more and more difficult to introduce hollow microspheres or foam dielectrics because the walls of the microspheres or the walls between air bubbles in the foam approach the dimension of the spaces between the conductor lines which is 1500A, 1000A, and eventually 500A.
Until recently in integrated circuit manufacturing, plated wiring was embedded in a dielectric material such as SiO2, polyimide, a combination of SiO2 and Si3O4, or other. One of the newer dielectric products is SiLK, a trademark product of Dow Chemical Company, which is a partially polymerized oligomeric spin-on material in a high purity NMP carrier solvent. The dielectric material provides electrical separation between and physical support for the individual conductor lines in the wiring levels. Support is particularly important in those structures which are built using a damascene process. Silicon dioxide has an Er of about 3.9 to about 4.5 and polyimide about 3.5, leaving room for improvement in current commercial structures as well as demanding improvement for structures of the future.
An article on pp. 575-585 published in the IBM Journal of Research and Development Volume 42 No. 5, September 1998, xe2x80x9cElectrochemical process for advanced package fabricationxe2x80x9d, coauthored by S. Krongelb, J. A. Tornello and L. T. Romankiw, the latter of whom is the inventor herein, includes a description of a process of making, and certain performance measurements of, a multilevel structure which incorporates polyimide dielectric layers and is on a chip carrier. In preparation for creating the scanning electron micrograph (SEM) images of the structure, seen as FIGS. 3 and 4 on p. 580 and FIG. 5 on p. 581, polyimide was removed from a region of the structure by ashing in an oxygen containing plasma. Electrical measurements were performed in order to ascertain that the metallurgy was sound and that good metal-to-metal contact had been obtained during electroplating. The present invention, in which solid dielectric material is replaced by air or vacuum in order to obtain a mechanically sound, multilevel final structure having minimal Er, was not foretold by the reference. Up to the time of the present invention it was assumed that dielectric such as polyimide would provide an minimum Er which would be adequate for the thin film package (chip carrier).
An article on pp. 49-51 published in the journal Electrochemical and Solid State Letters published by the Electrochemical Society, Inc., 1(1), 1998, xe2x80x9cAir-Gaps for electrical Interconnectionsxe2x80x9d is coauthored by Paul L. Kohl, Qiang Zhao, Kaushal Patel, Douglas Schmidt, Sue Ann Bidstrup-Allen, Robert Shick and S. Jayaraman. The reference describes the thermal decomposition of a sacrificial polymer at a temperature ramped up to 425 then to 450 degrees C. The sacrificial polymer is removed from between two metal line levels which are fully encapsulated within a permanent dielectric overcoat, and the products of the heat decomposition of the sacrificial polymer, less a thin residue, are forced out by diffusing through the overcoat, leaving a gap remaining in the region occupied by the polymer prior to its decomposition. It is stated in the reference that the effective dielectric constant between the two levels can be lowered to 2.3-2.7 for structures with a 1:1 aspect ratio (h:w), or perhaps lower, depending on the thickness and dielectric constant of the permanent overcoat. Clearly, the technique of thermal decomposition is quite different from that of the present invention. The feasibility of adapting and implementing a thermal decomposition technique in a manufacturing environment would be highly problematic. In order to manufacture a workable device it would be necessary to be able to fabricate more than two conductor line levels. That is would be possible to do so and to have the products of the heat decomposition of numerous levels of sacrificial polymer cleanly diffuse through multiple layers of permanent dielectric has not been described in the article.
A similar approach to the removal of sacrificial carbon or photoresist by heating in oxygen at about 400 to 450 degrees C. for 2 hours, during which CO2 diffuses out through silicon oxide is described in GB2,330,001A, which was published Apr. 7, 1999 by Shih-Wei Sun. In the GB patent the term xe2x80x9cashingxe2x80x9d is used for the removal process; in the electronics industry and in Applicant""s invention ashing means exposing a substance to be removed to an oxygen containing plasma.
In the Technology News column on page 38 of the March 1999 edition of the journal Semiconductor International, Editor-in-Chief Peter Singer describes Toshiba""s use of Carbon dioxide gas dielectric in the wiring level of a multilevel IC. Carbon dioxide is formed when the layer of carbon, which has been sputtered and covered with a thin layer of insulator is heated at 450 degrees C. in an oxygen atmosphere, resulting in the diffusion of oxygen through the thin layer of insulator and its combination with the underlying carbon to form carbon dioxide. Some key questions related to the workability of the resulting structure are identified. It appears from the example given that the process is performed one wiring level at a time, as only one such level is shown or described. It would be more efficient and practical if all levels to be hollowed were hollowed at one time, as in the present invention.
In an article xe2x80x9cFuture interconnect technologies and copper metallizationxe2x80x9d pages 63, 64, 68, 72, 74, 76 and 79 of the October, 1998 issue of the journal Solid State Technology, authors X, W. Lin and Dipu Pramanik describe a movement to electroplated copper wiring from aluminum wiring in the ICs of the future as an inevitable necessity. The authors further identify physical vapor deposited (PVD) or chemical vapor deposited (CVD) Ta, TaN, Si3N4 or W as known barriers to copper diffusion into silicon. Plated Cu is used in the present invention, in conjunction with diffusion barriers.
In an article xe2x80x9cair gaps lower k of interconnect dielectricsxe2x80x9d, pages 51, 52, 54, 57 and 58 of the February, 1999 issue of the journal Solid State Technology, authors Ben Shieh, Krishna Saraswat, Mike Deal and Jim McVittio describe results of their modelling of air or vacuum as a dielectric medium in a variety of conductor line dimensions. Their simulation predicts a 40%-50% reduction in capacitance due to air gaps in the aluminum wiring level. The article predicts a possible problem with thermal conductivity in an air dielectric-based structure, which may be ameliorated by having SiO2 or HSQ (hydrogen silesquioxane) in the via levels, and another possible problem of fracture of a multilevel structure during CMP (chemical metal polishing). The cover article xe2x80x9cIn-line cure of SOD low-k filmsxe2x80x9d, pages 29, 32 and 34 of the March, 1999 issue of the journal Solid State Technology, by Tom Batchelder, Wayne Cai, Jeff Bremmer and Doug Gray describes advantages of HSQ as a spin-on dielectric (SOD) due to the method of application being less complex and less expensive than CVD. A spin-on dielectric is a possible alternative permanent dielectric in the via levels of the present invention.
The present invention is unique in providing a functional multilevel chip structure which is mounted on a chip carrier, and a process for making the structure, in which an air, other suitable gas or an at least partial vacuum dielectric contributes to an Er which closely approaches the ideal value. In addition, the present invention provides enhanced cooling of the structure, reduced weight, circumvents thermal expansion mismatch problems, and obviates the need for any process steps related to the inclusion of fillers in dielectric material. In one example, a mechanically and electrically sound structure of up to eleven levels has been built successfully using air dielectric in both the wiring levels and the via levels. The resulting structure is not readily damaged or collapsed by application of reasonable pressure. In another structure of the present invention, in which diamond-like carbon (DLC) provides support in via levels, conductive lines in wiring levels having an air dielectric medium can be as close as 500 Angstroms apart.
In addition to lowering the Er, incorporating gas, such as air, inert gas, CO2, N2 or an at-least-partial vacuum dielectric medium into the structure of the present invention has the advantage of providing Er symmetry from level to level and across a level. In contrast to solid dielectric material, there is less likelihood of obtaining electrical anomalies due to the incorporation of conductive impurities or charged species. There is also less likelihood of XYZ dimensional distortion. Such dimensional instability can occur, for example, if a solid resinous dielectric material is exposed to temperatures at or above its glass transition temperature (Tg). Since areas of high mechanical stress are often sites at which electromigration is initiated, the fact that the conductive wiring is not confined within a solid dielectric can eliminate or reduce local stresses at corners and via/wiring intersections, hence reduce electromigration and electrical failure at the sites. The fact that joining of the chip to the carrier, such as by C4 or wire bonding, occurs before the removal of the temporary dielectric in Applicant""s invention enables a strong solder bond to be created while preventing the solder from leaking into the chip structure. The subsequent removal of the temporary dielectric occurs through the open sides of the chip structure.
The present invention is applicable to high performance chips, radio frequency (rf) chips, analog chips, high performance SRAM and DRAM, MEMS and especially to fabrication of metallurgical interconnects referred to as back-of-the-line (BEOL) for mounting on packaging substrates such as ceramic or FR4, for use in memory, logic devices, displays, computers other applications, present and future, that will be apparent to one skilled in the art. The principles of the present invention are suitable for use in a chip structure having any conductor metallurgy, including Cu, Al, Au, Ag or alloys thereof.
The present invention includes structures and processes useful for both thin film packages and multi-chip modules (MCM). The present invention provides a multilevel integrated wiring structure, and process of making the structure, which involves including a temporary dielectric material which, subsequent to dicing into chips and joining to a chip carrier, is readily and selectively removed, such as by dissolution or by ashing in an oxygen-containing or fluoride-containing atmosphere or plasma, depending on the composition of the sacrificial layers. Without compromising the integrity of the remaining structure, preselected levels are left having hollow areas to be filled with air or other suitable gas, or to be placed under at-least-partial vacuum, the gas or vacuum functioning as a permanent dielectric medium. Under the present invention, the electrically conducting columns, and xe2x80x9cdummyxe2x80x9d columns strategically placed uniformly throughout the chip and in the chip periphery also render strong mechanical support between wiring levels during the chemical mechanical polishing process (CMP) and subsequently in the completed chip and chip/carrier structure.
A structure has been fabricated having as many has 11 levels and an air dielectric medium in both the via and the wiring levels. Alternate structures under the present invention include solid permanent dielectric material in preselected via levels for additional support and the use of a silicon-containing dielectric material as a temporary dielectric in the place of a temporary resin resist dielectric.